1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory, and in particular, to a structure of a gate electrode.
2. Description of the Related Art
FIG. 1A is a plan view of a conventional NAND type nonvolatile semiconductor memory, FIG. 1B is a sectional view taken along the line 1B—1B in FIG. 1A, and FIG. 1C is a sectional view taken along the line 1C—1C in FIG. 1A. Note that FIGS. 1A to 1C respectively show points in time when a control gate (word line WL) of a memory cell transistor and a gate (select gate line SG) of a select transistor are formed.
Reference: S. Aritome et al, “A 0.67 μm2 SELF-ALIGNED SHALLOW TRENCH ISOLATION CELL (SA-STI CELL) FOR 3V-only 256 Mbit NAND EEPROMs”, IEDM, pp 61–64, 1994.
As shown in FIGS. 1A to 1C, shallow trench isolations (STIs) are formed as element isolation regions in a P-type well 101, and element regions are defined. Gate insulators 103 are formed on the element regions of the P-type well 101. Conductive polysilicon layers 105, an ONO film 113, and conductive polysilicon layers 115 are formed on the gate insulators 103.
The conductive polysilicon layers 105 form floating gates (FG) in the memory cell transistor (refer to FIG. 1B), and contact the conductive polysilicon layer 115 in a select transistor, and form portions of select gate lines SG (refer to FIG. 1C). Further, the conductive polysilicon layer 115 forms a word line WL (refer to FIG. 1B).
In this way, in the prior art, the word line WL and the select gate line SG are formed from the conductive polysilicon layers 115. Further, although not illustrated in particular, this prior art is formed from a structure in which a tungsten silicide layer is formed on the conductive polysilicon layer 115, i.e., a so-called a polycide structure.
Moreover, an example of a structural feature of the nonvolatile semiconductor memory shown in FIGS. 1A to 1C is that the conductive polysilicon layers 105 are divided by the STIs in a select transistor portion. Therefore, the ONO film 113 is removed from the select transistor portion, and the divided conductive polysilicon layers 105 are connected to each other by the conductive polysilicon layer 115, and the select gate line SG is formed (refer to FIG. 1C).
However, in order to remove the ONO film 113, a space Dcell-SG from the select gate line SG to the word line WL must be made broader than a space Dcell from the word line WL to the word line WL. The reason for this is that the alignment margin of the mask layer for removing the ONO film 113, and the alignment margin of the select gate SG and the portion at which the ONO film 113 is removed, respectively, must be anticipated.
Concretely, as shown in FIG. 2A and FIG. 2B, mask layers 141 for removing the ONO film 113 are offset within a range of “+X1” or “−X1” along the X direction from the forming target position. Accordingly, alignment margins of “+X1” and “−X1” from the forming target position are necessary.
Moreover, as shown in FIG. 3A and FIG. 3B, mask layers 119 for forming the word line WL and the select gate line SG are, in the same way, offset within a range of “+X2” or “−X2” along the X direction from the forming target position. Accordingly, alignment margins of “+X2” and “−X2” from the forming target position are necessary.
As a result, in order for the portion at which the ONO film 113 is removed to always be positioned under the mask layers 119, an alignment margin of “|X1|+|X2|” is necessary between the forming target position of the mask layers 114 and the forming target position of the mask layers 119.
However, in FIGS. 2A, 2B, 3A and 3B, because attention is focused on the alignment margin between the select gate line SG and the word line WL, an adjusting margin in the Y direction orthogonal to the X direction is ignored.
Further, a NAND type nonvolatile semiconductor memory as shown in FIGS. 4A to 4C has also been known.
Reference: Jpn. Pat. Appln. KOKAI Publication No. 11-26731 (U.S. Pat No. 6,342,715 B1)
FIG. 4A is a plan view, FIG. 4B is a sectional view taken along the line 4B—4B in FIG. 4A, and FIG. 4C is a sectional view taken along the line 4C—4C in FIG. 4A.
One of the main features of the device shown in FIGS. 4A to 4C is that the floating gates 105 have a double structure of a lower layer portion 105-1 and an upper layer portion 105-2. Further, the upper layer 105-2 spreads on the STIs, and the capacity between the control gates 115 (word lines WL) and the floating gates 105 is sufficiently larger than the capacity of the channels and the floating gates 105.
Moreover, in the select transistor portion, select gates SG are formed by the conductive polysilicon layers structuring the upper layer portions 105-2. In this way, the step of removing the ONO film 113 can be omitted.
However, in the device shown in FIGS. 4A to 4C, in the memory cell transistor portion, a so-called slit processing, for dividing the conductive polysilicon layer constituting the upper layer portions 105-2 for the respective memory cells, is necessary. Therefore, an alignment margin for the slit processing is firstly necessary. Moreover, an alignment margin, for exactly positioning the masks for select gate processing on the conductive polysilicon layers forming the upper layer portions 105-2 in which slits are not formed, is necessary.
Accordingly, even if the step of removing the ONO film 113 is eliminated, an alignment margin which is equivalent to that of the device shown in FIGS. 1A to 1C is necessary between the select gate lines SG and the word lines WL. As a result, in the device shown in FIG. 4A to 4C as well, the space Dcell-SG from the select gate line SG to the word line WL must be broader than the space Dcell from the word line WL to the word line WL.
In this way, in the conventional nonvolatile semiconductor memory, lowering of the resistance is attempted by structuring the word line WL and the select gate line SG from the conductive polysilicon layers 115, or from a polycide structure. However, as nonvolatile semiconductor memories have become smaller, it has become difficult to further lower the resistance.
Moreover, in the conventional nonvolatile semiconductor memory, in order to remove the ONO film 113 from the select transistor portion or in order to carry out slit processing, the space Dcell-SG from the select gate line SG to the word line WL must be broader than the space Dcell from the word line WL to the word line WL. This is an obstacle to further miniaturization of a nonvolatile semiconductor memory.